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[VHDL-FPGA-Verilog] risc-8

Description: 一个VHDL实现的RISC8位单片机-the RISC8 bit microcontrollers
Platform: | Size: 76800 | Author: 刘恩树 | Hits:

[VHDL-FPGA-Verilog] riscpu

Description: 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
Platform: | Size: 152576 | Author: 大为 | Hits:

[Other] ServoFundamentals

Description: 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM-chip applications and Selection
Platform: | Size: 132096 | Author: | Hits:

[VxWorks] VxWorks_DataCoherence

Description: VxWorks中主备数据一致性功能组件的设计与实现.pdf ：数据一致性是主备用系统必须解决的问题。目前主备 系统的一致性都采用手工编程来实现。导致代码结构繁杂， 且效率不高。利用VxWorks的异常处理机制，结合RISC CPU 的特性．设计实现了一个数据一致性功能组件。这个组件可 使数据的一致性处理自动化-VxWorks prepare data consistency in the main functional components of the Design and Implementation. Pdf: data consistency is the main backup system must be addressed. At present, the main preparation of the coherence of the system are used to achieve manual programming. Lead to complex code structure and inefficient. The use of VxWorks exception handling mechanism, combined with the characteristics of RISC CPU. Design and Implementation of a data consistency functional components. This component will enable the consistency of data automation deal
Platform: | Size: 124928 | Author: GB | Hits:

[VHDL-FPGA-Verilog] 16bit_cpu

Description: 16位的RISC_CPU， 应该对大家有帮助-16 of RISC_CPU, everyone should have to help
Platform: | Size: 439296 | Author: ekin | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[VHDL-FPGA-Verilog] freerisc8_11

Description: 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
Platform: | Size: 275456 | Author: wfs | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[Other] cputest

Description: 自己刚写的一个RISC的cpu，位宽16，主要是测试其中的逻辑，数据宽度是一位，可以很容易扩展-Writing just one of their own RISC the cpu, bit 16, are testing one of the main logic, data width, a, can be easily extended
Platform: | Size: 21504 | Author: myliu | Hits:

[Software Engineering] The_Simulation_and_Research_of_SkyEye_Bascd_on_ARM

Description: ARM作为一种32位精简指令集CPU，其结构已经从 V3发展到V6，在嵌入式应用领域获得了巨大的成功，并在 小体积、低功耗、低成本、高性能的嵌入式应用领域确立了 市场领导地位。基于ARM构建的硬件仿真环境一SkyEye， 是～个可以运行嵌入式操作系统的硬件仿真工具，它可以 在没有硬件条件下进行嵌入式系统的学习和开发-ARM is a 32-bit RISC CPU, its structure has been developed to V3 from V6, the field of embedded applications in a great success, and in a small volume, low-power, low-cost, high-performance embedded applications established a market leadership position. ARM-based hardware to build a simulation environment SkyEye, is a ~ can be embedded operating system to run the hardware simulation tool, it can in the absence of hardware for embedded systems under the conditions of learning and development
Platform: | Size: 133120 | Author: 任宪勇 | Hits:

[mpeg mp3] MB87L2250_datasheet

Description: Datasheet for MB87L2250 - MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU-Datasheet for MB87L2250- MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU
Platform: | Size: 129024 | Author: munche | Hits:

[Other] provide8bitRISCCPUbyFPGA

Description: 用FPGA制造一款8位RISC CPU出来，经典资料-Using FPGA to create an 8-bit RISC CPU out, classical information
Platform: | Size: 136192 | Author: narcissus.king | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: Verilog HDL编写的一个精简指令的处理器，很好用，可用来学习-Verilog HDL RISC_CPU
Platform: | Size: 14336 | Author: | Hits:

[Software Engineering] cpudesign

Description: Risc 32位CPU设计方法，由牛人主讲，可以好好学习-Risc 32 Wei CPU design methodology, from the cattle were speakers, you can learn
Platform: | Size: 292864 | Author: 孟天 | Hits:

[Windows Develop] cpudesign_doc

Description:
Platform: | Size: 292864 | Author: 孟天 | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[ARM-PowerPC-ColdFire-MIPS] S3C2440_H324

Description: 在现有的PSTN 网络上构建了一个嵌入式终端平台,该平台基于RISC 架构ARM 处理器S3C2440A,符合国际电联ITUT 建议的H.324 协议。此系统平台在原有的MCU+DSP 的架构基础上提出一种纯基于RISC 架构的ARM 处理器的可视电话 平台,该方案更加灵活, 可以用于现有的办公,家庭等环境.-Build a embedded platform of the ARM920T core RISC CPU S3C2440, which can connected to PSTN networks. This pure RISC system comply with the ITU-T H.324, developed from the MCU+ASIC and the MCU+DSP architecture, is more flexible. The VideoPhone based on this system could be widely used in the office and the house.
Platform: | Size: 217088 | Author: 张波 | Hits:

[Software Engineering] Application_Note_RTL8196B

Description: The RTL8192SE is an 802.11n single band (2.4GHz) 2T2R MAC/BB/RF in a single chip. The RTL8196B is a 5-port 10/100Mbps Ethernet switch embedded with a high performance 32-bit RISC CPU. The high integration of both chips provides a very competitive AP/Router solution.
Platform: | Size: 26624 | Author: forecast88 | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST
Platform: | Size: 328704 | Author: 魏文沫 | Hits:
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